One aspect of this invention relates to apparatus for sampling an analog signal voltage to provide charge packets the sizes of which are representative of successive samples. This apparatus comprises a semiconductor substrate of a given conductivity type within and adjacent a surface of which a charge carrier source region of the opposite conductivity type is provided and a channel region for transporting charge carriers from said source region is defined. The channel region has the given or the opposite conductivity type and has a plurality of gate electrodes insulatingly overlying it for controlling the charge carrier transport, said electrodes including a first gate electrode for forming a metering potential well within said channel region, a second gate electrode for forming a first potential barrier within said channel region between said metering potential well and said source region, and a third gate electrode for controlling the transfer of charge packets from said metering potential well towards an output. The apparatus further comprises an input for said analog signal voltage, which input is coupled to said first gate electrode, and a control signal generator arrangement coupled to said source region and to said first, second and third gate electrodes for applying a bias voltage in conjunction with said analog signal voltage to said first gate electrode so as to create said metering potential well, for applying a bias voltage to said second gate electrode so as to create said first potential barrier, and for applying clock signals having substantially the same phase to both said source region and said third gate electrode to control the potentials of the source region and the third gate electrode between (a) values at which said metering potential well will be filled over said first potential barrier with charge carriers from said source region to a level determined by the potential of said source region and said third gate electrode will create a second potential barrier acting to prevent said charge carriers from leaving said metering potential well, and (b) values at which said first potential barrier will act to prevent charge carriers entering the metering potential well from said source region and said third gate electrode will no longer create any potential barrier acting to prevent charge carriers leaving said metering potential well.
Another aspect of this invention relates to a method of sampling an analog signal voltage to provide charge packets the sizes of which are representative of successive samples, in which method a charge carrier source region of a given conductivity type provided within and adjacent a surface of a semiconductor substrate of the opposite conductivity type and a plurality of gate electrodes which insulatingly overly a charge carrier transport channel region of the given or the opposite conductivity type defined within said substrate adjacent said surface for controlling the transport of charge carriers from said source region through said channel region are controlled in a manner such that a metering potential well the depth of which depends on said analog signal voltage is created in said channel region by means of a first said gate electrode, a first potential barrier is created in said channel region between said well and said source region by means of a second said gate electrode, a second potential barrier is created in said channel region adjacent said metering potential well by means of a third said gate electrode, and said source region and said third gate electrode are controlled by clock pulses having substantially the same phase so that alternately (a) said metering potential well is filled over said first potential barrier with charge carriers from said source region to a potential level determined by the then potential of said source region while the second potential barrier is maintained sufficiently high to prevent such carriers from the source region from leaving the well, and (b) charge carriers are drained back from the well into the source region over the first potential barrier and, substantially simultaneously, the second potential barrier is lowered to allow charge carriers remaining in the well to leave the well towards an output.
Such an apparatus and method is known, for example, from an article entitled "Phase-Referred Input: A Simple New Linear C.C.D. Input method" by D. V. McCaughan and J. G. Harp in "Electronics Letters" Vol. 12 no. 25 (Dec. 9th, 1976) at page 682. This known apparatus and method employs a so-called "fill and spill" input method and, as will be evident from the title of the article, is used to input charge to a charge coupled device (CCD). An advantage of this known apparatus and method, as compared with other apparatuses and methods employing "fill and spill" input methods, is that it needs no special clock signals. The clock signals applied to the source region and the third gate electrode can be one and the same (albeit possibly with a d.c. bias on one relative to the other) and have a simple 1:1 mark-to-space ratio, whereas the bias voltages applied to the first and second gate electrodes can each be a simple d.c. bias.
The known apparatus is shown schematically in FIG. 1A of the accompanying diagrammatic drawings, FIGS. 1B, 1C and 1D illustrating various stages in the ideal operation thereof.
In FIG. 1A a semiconductor body or substrate 1, which is shown in a schematic cross-sectional view, has a major surface 2 on which is provided an electrically insulating layer 3. On the layer 3 are provided first, second and third gate electrodes 4,5 and 6, respectively, so that these electrodes overlie respective portions of a charge carrier transport channel region 7 defined at the surface 2 of the substrate 1 which is of a given conductivity type, for example, p-type. A charge carrier source region 10 of the substrate, adjoining the region 7, is of the opposite conductivity type, i.e. n-type in the present example, and provides the charge carriers transported by the region 7. A clock signal generator 11 supplies clock signals having a positive polarity (relative to the p-type region of the substrate 1) from an output 18 to the electrode 6 and the region 10. A d.c. voltage source 12 supplies a positive d.c. bias (relative to the p-type region of the substrate 1) from an output 23 to the electrode 5. Generator 11 and source 12 together constitute a control voltage generator arrangement 13. An output 24 of an analog input signal source 14 supplies a positive-polarity input signal to electrode 4 relative to electrode 5.
FIG. 1B illustrates the situation when the output of clock signal generator 11 is low (least positive). The positive potentials applied to the electrodes 4 and 5 result in the creation of a metering potential well 8 in the portion of region 7 under electrode 4 and a first potential barrier 9 in the portion of region 7 under electrode 5 respectively. The top of the barrier 9 corresponds to a potential V.sub.ref (determined by the output voltage of bias voltage source 12) and the bottom of well 8 corresponds to a potential V.sub.ref +V.sub.sig (determined by the output voltage of source 12 in conjunction with the output voltage of analog signal source 14). The potential V.sub.10 of n-type region 10 is less positive than V.sub.ref so that the metering potential well 8 under electrode 4 is filled over the first potential barrier 9 under electrode 5 with minority charge carriers (electrons in the present case, these being denoted by the shaded area 16) from the region 10, the filling being to the level V.sub.10. It will be noted that the potential V.sub.15 of the top of a second potential barrier formed under electrode 6 at this time is V.sub.x less positive than the level V.sub.10, so that this potential barrier acts to prevent electrons from leaving region 10.
Ignoring for the moment the dashed line 17 therein, FIG. 1C illustrates the situation at a point on the transition of the output signal of clock-signal generator 11 from low to high, more particularly the situation obtaining when the potential V.sub.10 of the region 10 has increased to that (V.sub.ref) of the top of the potential barrier 9 under electrode 5. All the electrons previously lying over this barrier have spilled back into the region 10, as have sufficient of those electrons previously in the metering potential well 8 under electrode 4 to leave the metering potential well filled to the level V.sub.ref. The number of electrons remaining in the metering potential well 8 is therefore representative of the value V.sub.sig of the output signal of source 14 at the relevant instant. It will be noted that the potential V.sub.15 of the top of the second potential barrier 15 is still V.sub.x less positive than the level V.sub.10, so that barrier 15 still acts to prevent electrons from leaving the well 8.
FIG. 1D illustrates the situation when the output of clock signal generator 11 has become high (most positive). The potential V.sub.15 of the top of the "barrier" 15 formed under electrode 6 is now sufficiently positive to ensure that this barrier no longer acts to prevent any electrons present in well 8 from leaving this well. All the electrons previously in the metering potential well 8 have drained into the region under electrode 6. (It is assumed for the purposes of the present discussion that a further potential barrier is present to the right of this region so that a potential well now exists under electrode 6. This may or may not be the case in practice, depending on the technique adopted for transferring charge from the region under electrode 6). Thus, a charge packet the size of which is representative of the value of the output voltage of source 14 at the instant to which FIG. 1C corresponds is now present in the portion of the region 7 under electrode 6, as required, and the various operations set forth above can now be repeated. It will be noted that, in the situation illustrated in FIG. 1D, the potential of the region 10 is more positive than the potential V.sub.ref of the top of the first potential barrier 9, so that barrier 9 acts to prevent electrons from entering the metering well 8 from the region 10 at this time.
The difference V.sub.x between the potentials V.sub.15 and V.sub.10 may be obtained by virtue of the particular construction adopted for the body 1 and its associated electrodes etc., or may be obtained by including a d.c. voltage source (not shown) in the connection from electrode 6 to region 10 in FIG. 1A.
As mentioned previously, FIGS. 1B, 1C and 1D illustrate ideal situations. Such ideal situations can in fact only be approached if sufficient time is available for a successful transition from each stage to the next because each transition involves the movement of electrons between regions of the body or substrate 1, and electrons, of course, do not have infinite mobilities. Making available such sufficient time involves imposing a limit on the steepness of the relevant edges of the clock pulses produced by generator 11 and hence on the maximum frequency thereof. If this is not done then inaccurate sampling of the output voltage of source 14 results, as is pointed out in, for example, the paragraph bridging columns 1 and 2 of U.S. Pat. No. 4,178,519. It is an object of the present invention to mitigate this disadvantage.